Borrow Save Adder Implementation Under Threshold Voltage Variability
DOI:
https://doi.org/10.22399/ijcesen.1004Keywords:
Monte Carlo simulations, variation-tolerant design, timing analysis, borrow-save, threshold voltage variationAbstract
It is commonly recognized that lower logic depth enables low voltage operation, which lowers power dissipation. But these circuits are especially prone to fluctuations, which could undermine the anticipated advantages. These short addresses the problem of increased threshold voltage variance by providing a low-power addition method that works under variability. In particular, by quantitatively comparing the effects of variation on the performances of ripple-carry adders (RCA) and borrow-save adders (BSA), the average power reduction that BSA achieves at low voltage values at the expense of increased delay variation is measured. This leads to a suggestion of a method that improves the performance of both adders. The calculated average power dissipation and maximum critical path delay variation of BSA at various supply voltages. It is demonstrated that a significant reduction in supply voltage is achievable, resulting reduction in BSA's overall power dissipation when compared to a counterpart operating at nominal voltage and maintaining a maximum delay lower than that of RCA. Moreover, straightforward design modifications that exchange latency for variability are incorporated in the BSA design, thereby lowering the maximum delay's normalized standard deviation.
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