Implementation of An Ultra-Low-Power High-Speed CLB Using A Memory Element And Its Power Dissipation Analysis for FPGA with Quantum-dot Cellular Automata
DOI:
https://doi.org/10.22399/ijcesen.1066Keywords:
QCA, DFF, CLB, LUT, MUX, FPGAAbstract
Quantum-dot Cellular Automata (QCA) was popular due to its very low power consumption and fast operating speed. QCA Designers are fascinated with developing and implementing nanoscale devices of digital circuits with rapid operating speed, low power consumption, and less area requirement. This paper describes an efficient layout design of CLB for FPGA implemented using Lookup Tables (LUTs) constructed by using efficient Multiplexers and DFF. A 4-input LUT is implemented using 2x1 multiplexers, and D Flip Flop is incorporated into the LUT to frame CLB. Programmable routing resources for signal propagation and control are done by quantum cells. The proposed D Flip Flop was implemented with an area-efficient and less delay requirement. The functionality of the D Flip Flop in the CLB was analyzed using the simulation results of the QCA Designer tool. It is implemented with 53 quantum cells in a small area of 0.07µm2 and a delay of one clock cycle. Furthermore, the flexible logic block developed using the proposed D Flip Flop structure has proven to be the best among existing modules. The CLB architecture has 655 quantum cells spread across 1.32 µm2 with three clock cycles delay and a power dissipation of 43. 33nW. It is clear that the present is a better and more effective solution in terms of area, complexity, cell count, and latency. The QCA Pro and QCA Designer software is used for all designs and simulation results.
References
Lent, C. S., Tougaw, P. D., Porod, W., & Bernstein, G. H. (1993). Quantum cellular automata. Nanotechnology, 4(1), 49.
Zokaa, S., & Gholami, M. (2018). Two Novel Flip Flop with Level Triggered Reset in Quantum Dot Cellular Automata. IJE TRANSACTIONS C: Aspects 31(53);415-421
Binaei, R., & Gholami, M. (2019). Design of multiplexer-based D flip-flop with set and reset ability in quantum dot cellular automata nanotechnology. International Journal of Theoretical Physics, 58(3), 687-699.
Vetteth, A., Walus, K., Dimitrov, V. S., & Jullien, G. A. (2003). Quantum-dot cellular automata of flip-flops. ATIPS Laboratory, 2500, 1-5.
Angizi, S., Moaiyeri, M. H., Farrokhi, S., Navi, K., & Bagherzadeh, N. (2015). Designing quantum-dot cellular automata counters with energy consumption analysis. Microprocessors and Microsystems, 39(7), 512-520.
Talamala, A., Patro, A. K., & Pinninti, K. (2023, July). Implementation of Optimized Logic Gate Circuits with Majority Voter using QCA Technology. In 2023 14th International Conference on Computing Communication and Networking Technologies (ICCCNT) (pp. 1-9). IEEE.
Hashemi, S., & Navi, K. (2012). New robust QCA D flip flop and memory structures. Microelectronics Journal, 43(12), 929-940.
Chakrabarty, R., Mahato, D. K., Banerjee, A., Choudhuri, S., Dey, M., & Mandal, N. K. (2018, January). A novel design of flip-flop circuits using quantum dot cellular automata (QCA). In 2018 IEEE 8th Annual computing and communication workshop and conference (CCWC) (pp. 408-414). IEEE.
Zoka, S., & Gholami, M. (2018). A novel rising edge triggered resettable D flip-flop using five input majority gate. Microprocessors and Microsystems, 61, 327-335
Sasamal, T. N., Singh, A. K., & Ghanekar, U. (2019). Design and implementation of QCA D-flip-flops and RAM cell using majority gates. Journal of Circuits, Systems and Computers, 28(05), 1950079.
Binaei, R., & Gholami, M. (2019). Design of novel D flip-flops with set and reset abilities in quantum-dot cellular automata nanotechnology. Computers & Electrical Engineering, 74, 259-272.
Sasamal, T. N., Singh, A. K., & Ghanekar, U. (2019). Design of QCA-based D Flip flop and memory cell using rotated majority gate. In Smart Innovations in Communication and Computational Sciences: Proceedings of ICSICCS 2017, Volume 2 (pp. 233-247). Springer Singapore.
Raj, M., Gopalakrishnan, L., Ko, S. B., Naganathan, N., & Ramasubramanian, N. (2020). Configurable logic blocks and memory blocks for beyond-CMOS FPGA-based embedded systems. IEEE Embedded Systems Letters, 12(4), 113-116.
Ajitha, D., Ahmed, S., Ahmad, F., & Rajini, G. K. (2021, March). Design of area efficient shift register and scan flip-flop based on QCA technology. In 2021 International Conference on Emerging Smart Computing and Informatics (ESCI) (pp. 716-719). IEEE.
Ghosh, B., Chandra, J. S., & Salimath, A. (2014). Design of a multi-layered QCA configurable logic block for FPGAs. Journal of Circuits, Systems and Computers, 23(06), 1450089.
Gudivada, A. A., & Sudha, G. F. (2022). Single-Precision Floating-Point Multiplier Design Using Quantum-Dot Cellular Automata with Power Dissipation Analysis. In Advances in Signal Processing and Communication Engineering: Select Proceedings of ICASPACE 2021 (pp. 103-116). Singapore: Springer Nature Singapore.
Gudivada, A. A., & Sudha, G. F. (2021). Novel optimized tree-based stack-type architecture for 2 n-bit comparator at nanoscale with energy dissipation analysis. The Journal of Supercomputing, 77, 4659-4680.
Gudivada, A. A., & Sudha, G. F. (2022). STQCA-FFT: A fast fourier transform architecture using stack-type QCA approach with power and delay reduction. Journal of Computational Science, 60, 101594.
Gudivada, A. A., & Sudha, G. F. (2022). Novel optimized low power design of single-precision floating-point adder using Quantum-dot Cellular Automata. The Journal of Supercomputing, 1-19.
Rahul SHANDILYA, & R.K. SHARMA. (2024). ProTECT: A Programmable Threat Evaluation and Control Unit for Zero Trust Networks. International Journal of Computational and Experimental Science and Engineering, 10(4). https://doi.org/10.22399/ijcesen.673
SHANDILYA, R., & SHARMA, R. (2024). FIS: A Programmable Multi-Bit Fault Injection Server for Embedded System. International Journal of Computational and Experimental Science and Engineering, 11(1). https://doi.org/10.22399/ijcesen.674
Bhavani, K. S., & Alinvinisha, V. (2015, March). Utilization of QCA based T flip flop to design counters. In 2015 International Conference on Innovations in Information, Embedded and Communication Systems (ICIIECS) (pp. 1-6). IEEE.
Downloads
Published
How to Cite
Issue
Section
License
Copyright (c) 2024 International Journal of Computational and Experimental Science and Engineering
This work is licensed under a Creative Commons Attribution 4.0 International License.
