Digital System Design of FPGA – Based UART Protocol Using Verilog HDL
DOI:
https://doi.org/10.22399/ijcesen.3306Keywords:
Baud rate, Asynchronous Transmitter/Receiver, Finite State Machine (FSM), Secure communicationAbstract
The paper centres on the design and implementation of a Universal Asynchronous Receiver/Transmitter (UART) communication protocol to efficiently send and receive 128-bit data with the aid of Verilog HDL, with verification carried out on a Field-Programmable Gate Array (ARTIX - 7 FPGA) platform. UART is a commonly used asynchronous serial communication protocol that facilitates data exchange between two devices via a straightforward two-wire interface (TX and RX) without necessitating a clock signal for synchronisation. The design comprises two primary elements: a transmitter unit that converts input data from a parallel structure to a serial configuration, including start and stop bits for synchronisation, and a receiver unit that captures the serial data, checks its accuracy, and transforms it back into a parallel format. A baud rate generator ensures reliable data transmission by producing consistent clock pulses, thus preventing data transmission rate discrepancies.
A thorough testbench is used to validate the system, simulating a range of transmission scenarios with distinct data values, start/stop bit configurations, and error states to verify proper operation. The system is synthesized and implemented on a field-programmable gate array (ARTIX - 7 FPGA), specifically the Xilinx Artix-7, to illustrate real-time functionality. Enhancing efficiency and scalability, the UART design increases the reliability of data transmission, thereby making it a versatile choice for various embedded communication systems.
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