Semiconductor Chip Design Compute jobs Errors and Warnings solutions provider based on Machine learning Prediction systems

Abstract

Significant error and warning data are generated by semiconductor physical design methods during the place-and-route process, which creates challenges and incurs significant costs in development time and impacts engineering productivity. Existing manual debugging methods require vast resources and can severely impact the time-to-market. This work presents an intelligent prediction method that uses machine learning algorithms to automatically predict and suggest a resolution for design errors during the synthesis, placement, clock tree synthesis, and routing phases of designs. The prediction system was built to operate seamlessly with widely-adopted EDA tools, such a Synopsys Fusion Compiler and Cadence Innovus, and can handle multi-dimensional information of timing violations, congestion patterns, power distribution, and design rule violations. The ability to use the latest multi-class classification and multi-output regression models allows the process of detecting errors and suggesting resolutions to occur before the design is complete for the four critical design processes. The framework shows substantial efficiencies over existing design cycle times and is particularly beneficial for complex designs that have multiple voltage domains, frequent power management requests, and mixed-signal technologies. The system has been implemented across several technology nodes and has proven to be robust and adaptive across the possible design work to be conducted. By leveraging an automated method, the need for design engineers to manually intervene in the design process was maintained while fulfilling industry design quality standards. In summary, the intelligent framework has turned the development process from reactive debugging into a preventative debugging model to provide a new platform for semiconductor design automation.