A Digital Phase Locked Loop Design from analysis to implementation : application to FSK demodulation
DOI:
https://doi.org/10.22399/ijcesen.3934Keywords:
Digital Phase-Locked Loop (DPLL), Phase Frequency Detector (PFD), Loop Filter (LF), Voltage Controlled Oscillator (VCO)Abstract
The study of Phase Locked Loops (PLL) has been heavily treated in literature and most of the theoretical and the analytical results of such are verified using simulations. Here we provide guidelines of a digital PLL design and his circuit implementation on Pspice simulator (16.6 version) for both analyzing and verifying the theoretical results. In fact, the digital PLL is a hybrid device where only the phase detector is built from a digital circuit and the remaining blocks are still analog ones.
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