High-Speed Functional Clocks Impact on Vmin (Minimum Operating Voltage) During Scan Testing and Methods to Reduce Vmin

Abstract

The Increased focus on Energy Efficiency within the manufacture of Semiconductors is the key leading focus of today's semiconductor manufacturing; voltage level affects equipment power consumption; longevity of that equipment; and ultimately, manufacturer's yield. High-speed functional clocks during scan testing create substantial challenges for voltage optimization. These clocks generate excessive switching activity that elevates voltage requirements beyond normal operational levels. The disparity between testing conditions and functional operation causes unnecessary yield loss. Good chips fail during manufacturing tests despite meeting all functional specifications. Clock gating architectures offer an effective solution to this challenge. Testpoint flops integrated into scan chains enable selective control of functional clock distribution. During capture cycles, strategic disabling of clock gating cells reduces switching activity in critical regions. Silicon validation on advanced process nodes confirms the effectiveness of this technique. Voltage requirements decrease substantially when functional clocks are appropriately managed. The technique scales effectively to future technology nodes where power density challenges intensify. Automated test pattern generation tools can optimize clock gating configurations to balance fault coverage with voltage constraints. The economic benefits are significant for high-volume production. Costs of manufacturing decrease directly due to an increased number of chips that meet voltage testing specifications.