Design and Analysis of Novel Full Adder using ECRAAL
DOI:
https://doi.org/10.22399/ijcesen.848Keywords:
Half Adder, Full Adder, Adiabatic Logic, Asy- chronous Adiabatic Logic, ECRL, digital circuitsAbstract
In VLSI (Very Large Scale Integration) design, adders are digital circuits that perform arithmetic operations, specifically addition, on binary numbers. They are used in many applications, including microprocessors, digital signal processors, and memory systems. An adder is composed of logic gates that take two binary numbers as inputs and produce a binary sum as output. In this paper we have designed and analysed A novel Full Adder circuit by using asychronous adiabatic Logic. ECRAAL means Efficient Charge Recovery Asychronous Adiabatic Logic which combines the ECRL and AAL. ECRAAL is used for implementing Full Adder circuit. The designed ECRAAL Full Adder circuit is compared with the existing ECRL adiabatic Logic in terms of speed, area and power. The Full Adder IS implemented by using TANNER Tools for 250nm Technology. The Novel Full adder has shown improvement in performance. It has decreased 14.71% average power and 50.49% maximum power as compared to ECRL.
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