Comparative Study of UVM and ML-Infused Methodologies for Next-Gen SoC Storage Verification

Abstract

It is a challenge to verify the high complexity of Storage controllers in System-on-Chip (SoC) designs. Universal Verification Methodology (UVM) is the de facto standard for functionally verifying these chips, but UVM suffers from fundamental limitations on modern Storage controllers that include complex NVMe protocols, multi-queue management, error correction, and power management states. ML-based verification methods, especially those utilizing extensions to the Portable Stimulus Standard, mark a new shift toward clever and data-driven methods for generating stimulus. These leverage Reinforcement Learning agents to solve for the best exploration policies, use Supervised Learning to predict the coverage impact of a simulation, and exploit Generative models to sample tests based on learned representations. Evaluations of real-world NVMe storage controller designs show that ML-improved methods can considerably reduce simulation time for high coverage. Furthermore, during late stages of verification, when naive random-based techniques show diminishing returns for convergence, the ML-based approach achieves statistically meaningful coverage improvement through learned coverage strategies without redundant tests. The method also discovers additional critical bugs in corner cases that are commonly missed by naive random-based verification techniques. Resource utilization analysis showed that although feature extraction and inference have some per-simulation overheads, due to a meaningful reduction in the number of simulations, the total cost in terms of computation and verification time is substantially reduced. The trained models are also transferable to other design variants with almost no retraining. The scalability studies show good scalability properties as design complexity increases, and the ML techniques were found to match the original performance benefits as the complexity increased. Overall, the results show that ML-assisted verification can complement conventional techniques and that hybrid flows utilizing existing infrastructure with tailored AI optimizations are practical for semiconductor enterprises to adopt.